The present application claims priority under 35 U.S.C. xc2xa7119 to Japanese Application No.2000-269588 filed on Sep. 6, 2000, which is hereby incorporated by reference in its entirely for all purposes.
1. Field of the Invention
The present invention relates to a method for manufacturing a nonvolatile A semiconductor memory device such as an EEPROM (Electrically Erasable Programmable Read Only Memory).
2. Description of the Related Art
An EEPROM is conventionally used as a nonvolatile semiconductor memory. FIG. 19, FIGS. 20(A) and (B) show a conventional memory cell of the EEPROM. FIG. 19 shows a top view, FIG. 20(A) shows a cross sectional view along Ixe2x80x94I line of FIG. 19, and FIG. 20(B) shows a cross sectional view along IIxe2x80x94II line of FIG. 19.
A memory cell of the nonvolatile semiconductor memory device has a stacked gate portion 200 as shown in FIG. 19 and FIG. 20(A). The memory cell has a diffusion portion 300, which is formed at a peripheral portion of the stacked gate portion 200 as shown in FIG. 19 and FIG. 20(B). A stacked gate is formed between isolation layers 102. The isolation layers 102 are formed over a p-type silicon substrate 100. The stacked gate portion 200 has a gate oxide layer 106, a first gate electrode (floating gate electrode) 108, an interelectrode dielectric layer 110, a second gate electrode (control gate electrode) 112, an intermediate insulating layer 114 and an interconnection 116. The gate oxide layer 106 is formed over the silicon substrate 100. The first gate electrode 108 is formed over the gate oxide layer 106. The interelectrode dielectric layer 110 is formed over the first gate electrode 108. The second gate electrode 112 is formed over the interelectrode dielectric layer 110. The intermediate insulating layer 114 is formed over the second gate electrode 112.
The diffusion portion 300 has the isolation layers 102, a diffusion layer 118, the gate oxide layer 106, the intermediate insulating layer 114 and a contact hole 120 as shown in FIG. 20(B). The diffusion layer 118 is formed in the silicon substrate 100. The gate oxide layer 106 is formed over the silicon substrate 100. The intermediate insulating layer 114 is formed over the isolation layers 102. An interconnecting metal is filled in the contact hole 120, and forms the interconnection 116.
FIGS. 21 (A)-23(H) show a method for manufacturing the conventional EEPROM. FIGS. 21(A)-(E), FIGS. 22(A)-(D) and FIGS. 23(A)-(D) correspond to line Ixe2x80x94I of FIG. 19. FIGS. 21(F)-(J), FIGS. 22(E)-(H) and FIGS. 23(E)-(H) correspond to line IIxe2x80x94II of FIG. 19.
The isolation layers 102 are formed over the silicon substrate 100. Active regions 200x and 300x are formed over the silicon substrate 100 in this process as shown in FIG. 21 (A) and FIG. 21(F). The gate oxide layer 106 is formed over active regions 200x and 300x as shown in FIG. 21(B) and FIG. 21(G). A first polysilicon layer 108x is formed over the isolation layer 102 and the gate oxide layer 106 as shown in, FIG. 21(C) and FIG. 21(H). The first polysilicon layer 108x is used as the first gate electrode 108.
A resist pattern 124 is formed over the first polysilicon layer 108x as shown in FIG. 21(D) and FIG. 21(l). The resist pattern 124 has an opening 122 over the isolation layer 102. An etching is performed using the resist pattern 124 as a mask. The first polysilicon layer 108x is separated in this etching as designed by reference number 108y shown in FIG. 21(E) and FIG. 21(J).
The interelectrode dielectric layer 110x is formed over the silicon substrate 100 after the resist pattern 124 is removed as shown in FIG. 22(A) and FIG. 22(E). A second polysilicon layer 112x is formed over the interelectrode dielectric layer 110x as shown in FIG. 22(B) and FIG. 22(F).
A resist pattern 126 is formed over the stacked gate portion 200x as shown in FIG. 22(C) and FIG. 22(G). An etching is performed using the resist pattern 126 as a mask. The second polysilicon layer 112x over the diffusion portion 300x is removed by this etching as shown in FIG. 22(H), and the second polysilicon layer 112 formed over the stacked gate portion 200x remains as shown in FIG. 22(D). Then, etchings are performed using the resist pattern 126 as a mask. The interelectrode dielectric layer 110x and the first polysilicon layer 108y over the diffusion portion 300x are removed, as shown in FIGS. 23(A), (B), (E) and (F).
The resist pattern 126 is removed, and an implantation of ions (for example As) is performed. Then, a thermal diffusion is performed. The diffusion layer 118 at the diffusion portion 300x is formed by this process as shown in FIG. 23(C) and FIG. 23(G). A BPSG (Boron-Phosphate-Silicate-Glass) layer as the intermediate insulating layer 114 is formed over the silicon substrate 100. A resist pattern (not shown in FIG. 23) is formed over the intermediate insulating layer. The resist pattern has an opening over the diffusion layer 118. An etching is performed using the resist pattern as a mask. This etching forms the contact hole 120 as shown in FIG. 23(D) and FIG. 23(H). The contact hole 120 is filled a metal layer. The metal layer is also formed over the intermediate insulating layer 114. The metal layer is patterned according to a pattern of the interconnect 116.
However, in the conventional nonvolatile semiconductor memory device, a concave portion is formed in the isolation layer 102 of the diffusion portion 300 during the etching of the interelectrode dielectric layer 110. Therefore, ions are introduced under the isolation layer 102. This causes a formation of an unnecessary diffusion layer 128, and adjacent diffusion portions are connected each other.
A method for manufacturing a semiconductor memory device includes forming an isolation layer over a semiconductor substrate having a stacked gate region and a diffusion region, the isolation layer is formed adjacent the diffusion region of the semiconductor substrate. The method further includes forming a gate oxide layer over the gate stacked region, forming a first conductive layer over the isolation layer, the gate oxide layer and the diffusion region, forming a nitride layer over the first conductive layer the nitride layer having an opening at the isolation layer, forming an oxide region in the first conductive layer using the nitride layer as a mask, removing the nitride layer and the silicon oxide region, forming an interelectrode dielectric layer over the first conductive layer, forming a second conductive layer over the interelectrode dielectric layer, the second conductive layer over the diffusion portion, removing the interelectrode dielectric layer over the diffusion portion, removing the first conductive layer over the diffusion portion and forming diffusion layer in the silicon substrate of the diffusion portion.